1. Field of the Invention
The present invention relates to proprietary circuit layouts. More particularly, this invention relates to the identification of the use of a proprietary circuit layout.
2. Description of the Prior Art
The owners of proprietary circuit layouts may wish to gather royalty payments from those who choose to design, manufacture and/or use circuitry incorporating such proprietary circuit layouts. However, whilst most manufacturers and end users will make royalty payments to the owner fairly corresponding to their usage of these proprietary circuit layouts, the complexity of modem circuit designs may mean that some royalties are not gathered, due to the difficulties of tracking the usage of particular proprietary circuit layouts.
For this reason, in order to seek to identify usage of their proprietary circuit layouts, it is known for proprietary circuit layout owners to add information to their circuit layouts which will enable them later to readily identify a given circuit as containing one or more of their proprietary circuit layouts. For example, a circuit designer who issues circuit layouts in the form of an IP library may embed tagging data within the circuit layouts held in that IP library, relying on techniques for identifying that embedded tagging data at a later stage in the circuit production process to identify usage of their proprietary circuit layouts. Such a technique is described in the document “Virtual Component Identification Physical Tagging Standard 1.3.0 Revision 3.0 Released Jun. 2006. However, a significant drawback of this technique is that the end user, the foundry or integrated device manufacturer (IDM) can inadvertently remove this tagging data, or even intentionally remove it, such that identification of the proprietary circuit layout by this method is not possible thereafter.
An alternative technique for embedding tagging information is “watermarking” such as that described in “VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images”, Garimella et al., VLSID pp. 283, 16th International Conference on VLSI Design, 2003-1063-9667/03 IEEE. This describes a method of adding information to proprietary digital content to identify the owner of that digital content.
All such prior art techniques suffer from the same fundamental disadvantage, that tagging data or watermarks must not only be added in the first place, but can still be removed either accidentally or intentionally, and the circuit designer then loses the ability to track use of his proprietary circuit layouts for royalty purposes.
Hence, it would be desirable to provide an improved technique for identifying use of proprietary circuit layouts.